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terrestrial fpga and soc product catalog october 2011 power matters.
www .microsem i.com /soc the leader in customizable system-on-chip devices and fpgas for sense and control applications where reliability , security, and power matter.
3 www .microsem i.com /soc whether youre designing at the board or system level, microsemis customizable system-on-chip (csoc) devices and low power fpgas are your best choice. the unique, fash-based technology of microsemi fpgas, coupled with their history of reliability, sets them apart from traditional fpgas. design for todays rapidly growing markets of consumer and portable medical devices, or tomorrows environmentally friendly data centers, industrial controls and military and commercial aircraft. only microsemi can meet the power, size, cost and reliability targets that reduce time-to-market and enable long-term proftability. now, more than ever, power matters. table of contents smartfusion ? ? customizable system-on-chip (csoc) 4 fusion ? mixed signal fpgas 5 extended temperature fusion ? mixed signal integration down to C55oc ? reprogrammable digital logic and confgurable analog ? embedded flash memory 6 igloo ? /e ? low power ? small package footprint ? high logic density 7 igloo nano ? low power ? small package footprint 8 igloo plus ? low power ? small package footprint ? high i/o-to-logic ratio 9 proasic ? 3/e ? high logic density ? high performance ? low cost 10 proasic3 nano ? small package footprint ? high performance ? low cost 11 proasic3l ? low power ? high logic density ? high performance ? low cost 12 military proasic3/el ? unprecedented low power consumption across the full military temperature range ? high-density fine-pitch ball grid packaging ? high performance and easy in-system programming 13 military proasic plus? ? industrys first military screened flash fpga ? full processing to mil-std-883 class b ? established heritage on commercial and military aircraft 13 i/o table ? i/o counts 14 fpga packages ? package dimensions 16 axcelerator ? 18 sx-a 19 mx 20 design tools ? design environment for microsemi flash devices 21 development kits ? starter, evaluation and demonstration kits 22 programmers ? flashpro3 and silicon sculptor 3 programmers 26 intellectual property cores ? microsemi ip cores 27 please refer to www.microsemi.com/soc and appropriate product datasheets for the latest device information, valid ordering codes and more information regarding previous generations of fash and antifuse fpgas.
4 www .microsem i.com /soc smartfusion the customizable system-on-chip (csoc) device smartfusion csocs are the only devices that integrate fpga fabric, an arm ? cortex ? -m3 processor and programmable analog, offering full customization, ip protection and ease-of-use. based on microsemis proprietary fash process, smartfusion csocs are ideal for hardware and embedded designers who need a true system-on-chip that gives more fexibility than traditional fxed-function microcontrollers without the excessive cost of soft processor cores on traditional fpgas. ? available in commercial, industrial and military* grades ? hard 100 mhz 32-bit arm cortex-m3 cpu ? multi-layer ahb communications matrix with up to 16 gbps throughput ? 10/100 ethernet mac ? two peripherals of each type: spi, i 2 c, uart, and 32-bit timers ? up to 512 kb fash and 64 kb sram ? external memory controller (emc) ? 8-channel dma controller ? integrated analog-to-digital converters (adcs) and digital- to-analog converters (dacs) with 1 percent accuracy ? on-chip voltage, current and temperature monitors ? up to ten 15 ns high-speed comparators ? analog compute engine (ace) offoads cpu from analog processing ? up to 35 analog i/os and 169 digital gpios * under development smartfusion devices notes: 1. not available on a2f500 for the pq208 package. 2. two plls are available in cs288 and fg484 (one pll in fg256 and pq208). 3. these functions share i/o pins and may not all be available at the same time. 4. available on fg484 only. pq208, fg256, and cs288 packages offer the same programmable analog capabilities as a2f200. notes: 1. these pins are shared between direct analog inputs to the adcs and voltage/current/temperature monitors. 2. 16 mss i/os are multiplexed and can be used as fpga i/os, if not needed for the mss. these i/os support schmitt triggers and support only lvttl and lvcmos (1.5 / 1.8 / 2.5, 3.3 v) standards. 3. 9 mss i/os are primarily for 10/00 ethernet mac and are also multiplexed and can be used as fpga i/os if ethernet mac is not used in a design. these i/os support schmitt triggers and support only lvttl and lvcmos (1.5 / 1.8 / 2.5, 3.3 v) standards. 4. 10/100 ethernet mac is not available on a2f060. 5. emc is not available on the a2f500 pq208 package. package i/os: mss + fpga i/os smartfusion devices a2f060 a2f200 a2f500 fpga fabric system gates 60,000 200,000 500,000 tiles (d-fip-fops) 1,536 4,608 11,520 ram blocks (4,608 bits) 8 8 24 microcontroller subsystem (mss) flash (kbytes) 128 256 512 sram (kbytes) 16 64 64 cortex-m3 with memory protection unit (mpu) yes yes yes 10/100 ethernet mac no yes yes external memory controller (emc) 24-bit address, 16-bit data 24-bit address, 16-bit data 24-bit address, 16-bit data 1 dma 8 ch 8 ch 8 ch i 2 c 2 2 2 spi 2 2 2 16550 uart 2 2 2 32-bit timer 2 2 2 pll 1 1 2 2 32 khz low power oscillator 1 1 1 100 mhz on-chip rc oscillator 1 1 1 main oscillator (32 khz to 20 mhz) 1 1 1 programmable analog adcs (8-/10-/12-bit sar) 1 2 3 4 dacs (12-bit sigma-delta) 1 2 3 4 signal conditioning blocks (scbs) 1 4 5 4 comparators 3 2 8 10 4 current monitors 3 1 4 5 4 temperature monitors 3 1 4 5 4 bipolar high voltage monitors 3 2 8 10 4 device a2f060 a2f200 a2f500 tq144 cs288 fg256 pq208 cs288 fg256 fg484 pq208 cs288 fg256 fg484 direct analog input 11 11 11 8 8 8 8 8 8 8 12 shared analog input 1 4 4 4 16 16 16 16 16 16 16 20 total analog input 15 15 15 24 24 24 24 24 24 24 32 total analog output 1 1 1 1 2 2 2 1 2 2 3 mss i/os 2,3 21 4 28 4 26 4 22 31 25 41 22 31 25 41 fpga i/os 33 68 66 66 78 66 94 66 5 78 66 128 total i/os 70 112 108 113 135 117 161 113 135 117 204 smartfusion
5 www .microsem i.com /soc ? integrated a/d converter (adc) with 8-, 10- and 12-bit resolution and 30 scalable analog input channels ? adc accuracy better than 1 percent ? on-chip voltage, current and temperature monitors ? in-system confgurable analog supports a wide variety of applications ? up to 1 mb of user fash memory ? extensive clocking resources ? analog plls ? 1 percent rc oscillator ? crystal oscillator circuit ? real-time counter (rtc) ? flash fpga fabric ? reprogrammable ? live at power-up ? maximum design security ? ultra-low power ? confguration memory error immune ? clock management ? advanced i/o standards ? user nonvolatile flashrom notes: 1. refer to the cortex-m1 product brief for more information. 2. pigeon point devices only offered in fg484 and fg256 packages. 3. microblade devices only offered in fg256 package. notes: 1. pigeon point devices only offered in fg484 and fg256 packages. 2. microblade devices only offered in fg256 package. 3. these packages are available only as rohs-compliant (qng package specifer). 4. afs250 and afs600 pq208 devices are not pin-compatible. 5. available in rohs-compliant and standard leaded packages. fusion package i/os: single-/double-ended (analog) fusion mixed signal fpgas afs090 afs250 afs600 afs1500 cortex-m1 devices m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 1 p1afs1500 1 microblade devices u1afs600 2 qn108 3 37/9 (16) qn180 3 60/16 (20) 65/15 (24) pq208 4 93/26 (24) 95/46 (40) fg256 5 75/22 (20) 114/37 (24) 119/58 (40) 119/58 (40) fg484 5 172/86 (40) 223/109 (40) fg676 5 252/126 (40) fusion devices the worlds frst mixed signal fpga fusion fpgas integrate confgurable analog, large fash memory blocks, comprehensive clock generation and management circuitry and high-performance, fash-based programmable logic in a monolithic device. the fusion architecture can be used with soft microcontroller cores, such as the performance-optimized arm cortex-m1, 8051s or microsemis own coreabc, the smallest soft microcontroller for fpgas. fusion devices afs090 afs250 afs600 afs1500 cortex-m1 devices 1 m1afs250 m1afs600 m1afs1500 pigeon point devices p1afs600 2 p1afs1500 2 microblade devices u1afs600 3 general information system gates 90,000 250,000 600,000 1,500,000 tiles (dCfipCfops) 2,304 6,144 13,824 38,400 aes-protected isp yes yes yes yes plls 1 1 2 2 globals 18 18 18 18 memory flash memory blocks (2 mbits) 1 1 2 4 total flash memory bits 2 m 2 m 4 m 8 m flashrom bits 1,024 1,024 1,024 1,024 ram blocks (4,608 bits) 6 8 24 60 ram (kbits) 27 36 108 270 analog and i/os analog quads 5 6 10 10 analog input channels 15 18 30 30 gate driver outputs 5 6 10 10 i/o banks (+ jtag) 4 4 5 5 maximum digital i/os 75 114 172 252 analog i/os 20 24 40 40 fusion
6 www .microsem i.com /soc extended temperature fusion devices afs600 afs1500 cortex-m1 devices m1afs600 m1afs1500 system gates 600,000 1,500,000 tiles (dCfipCfops) 13,824 38,400 aes-protected isp yes yes plls 2 2 globals 18 18 flash memory blocks (2 mbits) 2 4 total flash memory bits 4 m 8 m flashrom bits 1,024 1,024 ram blocks (4,608 bits) 24 60 ram (kbits) 108 270 analog quads 10 10 analog input channels 30 30 gate driver outputs 10 10 i/o banks (+ jtag) 5 5 maximum digital i/os 172 223 analog i/os 40 40 package pins fg fg256, fg484 fg256, fg484 extended temperature fusion mixed signal integration at extended temperatures microsemi fusion mixed signal fpgas integrate confgurable analog, large fash memory blocks, comprehensive clock generation and management circuitry and high-performance, fash-based reprogrammable logic in a monolithic device. innovative fusion architecture can be used with microsemis soft microcontroller (mcu) core as well as the performance-maximized 32-bit arm cortex- m1 cores. extended temperature fusion devices operate at temperatures from 100oc to as low as -55oc. extended temperature fusion devices extended temperature fusion
7 www .microsem i.com /soc igloo ? ultra low power fpgas ? flash*freeze technology for lowest power consumption ? 1.2 v core and i/o voltage ? 5 w flash*freeze mode ? reprogrammable ? live at power-up ? aes-protected in-system programming (isp) ? user nonvolatile flashrom igloo/e notes: s ot e o ote ees oes ot sot te tee t o etos e e o ees oe e ee oes ot sot ts e igloo/e devices notes: e ee oes ot sot n o es se eet ees te e o seee s e to i/os per package igloo devices agl030 agl060 agl125 agl250 agl400 agl600 agl1000 agle600 agle3000 cortex-m1 devices m1agl250 1 m1agl600 m1agl1000 m1agle3000 i/o type single- ended i/o single- ended i/o single- ended i/o single- ended i/o 2 differen- tial i/o pairs single- ended i/o 2 differen- tial i/o pairs single- ended i/o 2 differen- tial i/o pairs single- ended i/o 2 differen- tial i/o pairs single- ended i/o 2 differen- tial i/o pairs single- ended i/o 2 differen- tial i/o pairs qn48 34 qn68 49 uc81 66 cs81 66 cs121 96 vq100 77 71 71 68 13 qn132 81 80 84 87 19 cs196 133 143 35 143 35 fg144 96 97 97 24 97 25 97 25 97 25 fg256 178 38 177 43 177 44 165 79 cs281 215 53 215 53 fg484 194 38 235 60 300 74 270 135 341 168 fg896 620 310 the ultra low power programmable solution the igloo family of reprogrammable, full-featured fash fpgas is designed to meet the demanding power, area and cost requirements of todays portable electronics. based on nonvolatile fash technology, the 1.2 v to 1.5 v operating voltage family offers the industrys lowest power consumptionas low as 5 w. the igloo family supports up to 3,000,000 system gates with up to 504 kbits of true dual-port sram, up to 6 embedded plls and up to 620 user i/os. low power applications that require 32-bit processing can use the arm cortex-m1 processor without license fee or royalties in m1 igloo devices. developed specifcally for implementation in fpgas, cortex-m1 offers an optimal balance between performance and size to minimize power consumption. igloo devices agl030 agl060 agl125 agl250 agl400 agl600 agl1000 agle600 agle3000 cortex-m1 devices 1 m1agl250 m1agl600 m1agl1000 m1agle3000 system gates 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000 600,000 3,000,000 typical equivalent macrocells 256 512 1,024 2,048 versatiles (d-fip-fops) 768 1,536 3,072 6,144 9,216 13,824 24,576 13,824 75,264 flash*freeze mode (typical, w) 5 10 16 24 32 36 53 49 137 ram (1,024 bits) 18 36 36 54 108 144 108 504 ram blocks (4,608 bits) 4 8 8 12 24 32 24 112 flashrom kbits (1,024 bits) 1 1 1 1 1 1 1 1 1 aes-protected isp 1 yes yes yes yes yes yes yes yes integrated plls with ccc 2 1 1 1 1 1 1 6 6 versanet globals 3 6 18 18 18 18 18 18 18 18 i/o banks 2 2 2 4 4 4 4 8 8 maximum user i/os (packaged device) 81 96 133 143 194 235 300 270 620 package pins uc cs qn vq fg uc81 cs81 qn48 qn68 qn132 vq100 cs121 qn132 vq100 fg144 5 cs81 cs196 qn132 vq100 fg144 cs81 cs196 4 qn132 4 vq100 fg144 cs196 fg144 fg256 fg484 cs281 fg144 fg256 fg484 cs281 fg144 fg256 fg484 fg256 fg484 fg484 fg896
8 www .microsem i.com /soc igloo ? ultra low power in flash*freeze mode, as low as 2 w ? variety of small footprint packages as small as 3x3 mm ? zero lead-time on selected devices ? known good die supported ? enhanced commercial temperature ? reprogrammable fash technology ? 1.2 v to 1.5 v single voltage operation ? enhanced i/o features ? clock conditioning circuits (cccs) and plls ? embedded sram and nonvolatile memory (nvm) ? isp and security igloo nano igloo nano devices i/os per package igloo nano devices agln010 agln020 agln060 agln125 agln250 known good die 34 52 71 71 68 uc36 23 qn48 34 qn68 49 uc81 52 cs81 52 60 60 60 vq100 71 71 68 the industrys lowest power, smallest-size solution igloo nano products offer groundbreaking possibilities in power, size, lead-times, operating temperature and cost. available in logic densities from 10,000 to 250,000 gates, the 1.2 v to 1.5 v igloo nano devices have been designed for high-volume applications where power and size are key decision criteria. igloo nano devices are perfect asic or assp replacements, yet retain the historical fpga advantages of fexibility and quick time-to-market in low power and small footprint profles. notes: n se ees o ot sot ts ete n n n te e o ot sot s o e estes sot o to etes ee to te e tseets ses es note: e te seee s se to et ee seee oe ot se s e te e o seee se s e s ee oe igloo nano devices agln010 agln020 agln060 agln125 agln250 system gates 10,000 20,000 60,000 125,000 250,000 typical equivalent macrocells 86 172 512 1,024 2,048 versatiles (d-fip-fops) 260 520 1,536 3,072 6,144 flash*freeze mode (typical, w) 2 4 10 16 24 ram kbits 1 (1,024 bits) 18 36 36 4,608-bit blocks 1 4 8 8 flashrom kbits (1,024 bits) 1 1 1 1 1 aes-protected isp 1 yes yes yes integrated pll in cccs 1,2 1 1 1 versanet globals 4 4 18 18 18 i/o banks 2 3 2 2 4 maximum user i/os (packaged device) 34 52 71 71 68 known good die user i/os 34 52 71 71 68 package pins uc cs qn vq uc36 qn48 uc81 cs81 qn68 cs81 vq100 cs81 vq100 cs81 vq100
9 www .microsem i.com /soc igloo igloo plus igloo plus devices i/os per package igloo plus devices aglp030 aglp060 aglp125 system gates 30,000 60,000 125,000 typical equivalent macrocells 256 512 1,024 versatiles (d-fip-fops) 792 1,584 3,120 flash*freeze mode (typical, w) 5 10 16 ram (1,024 bits) 18 36 4,608-bit blocks 4 8 flashrom kbits (1,024 bits) 1 1 1 aes-protected isp yes yes integrated pll in cccs 1 1 1 versanet globals 2 6 18 18 i/o banks 4 4 4 maximum user i/os (packaged device) 120 157 212 package pins cs vq cs201, cs289 vq128 cs201, cs289 vq176 cs281, cs289 igloo plus devices aglp030 aglp060 aglp125 i/o type single-ended i/o single-ended i/o single-ended i/o cs201 120 157 cs281 212 cs289 120 157 212 vq128 101 vq176 137 the low power fpga with enhanced i/o capabilities igloo plus products deliver unrivaled low power and i/o features in a feature-rich programmable device, offering up to 64 percent more i/os than the award-winning igloo products and supporting independent schmitt trigger inputs, hot-swapping and flash*freeze bus hold. ranging from 30,000 to 125,000 gates, the 1.2 v to 1.5 v igloo plus devices have been optimized to meet the needs of i/o -intensive, power-conscious applications that require exceptional features. ? i/o-optimized fpga ? ultra low power in flash*freeze mode, as low as 5 w ? low power active capability ? small footprint and low-cost packages ? reprogrammable fash technology ? 1.2 v to 1.5 v single voltage operation ? enhanced i/o features ? cccs and plls ? embedded sram nvm ? aes-protected isp ? notes: oes ot sot te tee t o etos e e o ? note: e te seee s se to et ee seee oe ot se s e te e o seee se s e s ee oe
10 proasic3 proasic3/e i/os per package the low power, low-cost fpga solution the proasic3 series of fash fpgas offers a breakthrough in power, price, performance, density and features for todays most demanding high-volume applications. proasic3 devices support the arm cortex-m1 processor, offering the benefts of programmability and time-to-market at low cost. proasic3 devices are based on nonvolatile fash technology and support 30,000 to 3,000,000 gates and up to 620 high-performance i/os. for automotive appli cations, selected proasic3 devices are qualifed to the aec-q100 and are available with aec t1 screening and ppap documentation. proasic3 devices a3p030 a3p060 a3p125 a3p250 a3p400 a3p600 a3p1000 a3pe600 a3pe1500 a3pe3000 cortex-m1 devices m1a3p250 * m1a3p400 m1a3p600 m1a3p1000 m1a3pe1500 m1a3pe3000 i/o type single- ended i/o single- ended i/o single- ended i/o single- ended i/o differen- tial i/o pairs single- ended i/o differen- tial i/o pairs single- ended i/o differen- tial i/o pairs single- ended i/o differen- tial i/o pairs single- ended i/o differen- tial i/o pairs single- ended i/o differen- tial i/o pairs single- ended i/o differen- tial i/o pairs qn48 34 qn68 49 qn132 81 80 84 87 19 cs121 96 vq100 77 71 71 68 13 tq144 91 100 pq208 133 151 34 151 34 154 35 154 35 147 65 147 65 147 65 fg144 96 97 97 24 97 25 97 25 97 25 fg256 157 38 178 38 177 43 177 44 165 79 fg324 221 110 fg484 194 38 235 60 300 74 270 135 280 139 341 168 fg676 444 222 fg896 620 310 notes: s ot e o ote o ees e s toote e e ee oes ot sot ts e note: oes ot sot te n es proasic3/e devices a3p030 a3p060 a3p125 a3p250 a3p400 a3p600 a3p1000 a3pe600 a3pe1500 a3pe3000 cortex-m1 devices m1a3p250 m1a3p400 m1a3p600 m1a3p1000 m1a3pe1500 m1a3pe3000 system gates 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000 600,000 1,500,000 3,000,000 typical equivalent macrocells 256 512 1,024 2,048 versatiles (d-fip-fops) 768 1,536 3,072 6,144 9,216 13,824 24,576 13,824 38,400 75,264 ram (1,024 bits) 18 36 36 54 108 144 108 270 504 4,608-bit blocks 4 8 8 12 24 32 24 60 112 flashrom kbits (1,024 bits) 1 1 1 1 1 1 1 1 1 1 aes-protected isp 1 yes yes yes yes yes yes yes yes yes integrated pll in cccs 1 1 1 1 1 1 6 6 6 versanet globals 6 18 18 18 18 18 18 18 18 18 i/o banks 2 2 2 4 4 4 4 8 8 8 maximum user i/os (packaged device) 81 96 133 157 194 235 300 270 444 620 package pins qfn cs vq tq pq fg qn48 qn68 qn132 vq100 qn132 cs121 vq100 2 tq144 fg144 2 qn132 2 vq100 2 tq144 pq208 fg144 2 qn132 2, 3 vq100 2 pq208 fg144 2 fg256 2, 3 pq208 fg144 fg256 fg484 pq208 fg144 fg256 fg484 pq208 fg144 2 fg256 2 fg484 2 pq208 fg256 fg484 pq208 fg484 fg676 pq208 fg324 fg484 fg896 ? low power ? single chip, single voltage ? nonvolatile, reprogrammable ? low cost ? live at power-up ? maximum design security ? confguration memory error immune ? clock management ? advanced i/o standards ? user nonvolatile flashrom ? secure isp ? high performance proasic3/e devices
11 www .microsem i.com /soc proasic3 proasic3 nano the lowest-cost solution with enhanced i/o capabilities microsemis innovative proasic3 nano devices bring a new level of value and fexibility to high-volume markets. when measured against the typical project metrics of performance, cost, fexibility and time-to-market, proasic3 nano devices provide an attractive alternative to asics and assps in fast moving or highly competitive markets. customer-driven total system cost reduction was a key design criterium for the proasic3 nano program. reduced device cost, availability of known good die, a single-chip implementation and a broad selection of small footprint packages all contribute to lower total system costs. ? 1.5 v core for low power ? known good die supported ? 350 mhz system performance ? embedded sram nvm ? confguration memory error immune ? enhanced commercial temperature ? enhanced i/o features ? isp and security ? reprogrammable fash technology ? zero lead-time on selected devices ? cccs and plls i/os per package proasic3 nano devices proasic3 nano devices a3pn010 a3pn020 a3pn060 a3pn125 a3pn250 system gates 10,000 20,000 60,000 125,000 250,000 typical equivalent macrocells 86 172 512 1,024 2,048 versatiles (d-fip-fops) 260 520 1,536 3,072 6,144 ram 1 (1,024 bits) 18 36 36 4,608-bit blocks 1 4 8 8 flashrom kbits (1,024 bits) 1 1 1 1 1 aes-protected isp 1 yes yes yes integrated pll in cccs 1 1 1 1 versanet globals 4 4 18 18 18 i/o banks 2 3 2 2 4 maximum user i/os (packaged device) 34 49 71 71 68 known good die user i/os 34 52 71 71 68 package pin qn vq qn48 qn68 vq100 vq100 vq100 proasic3 nano devices a3pn010 a3pn020 a3pn060 a3pn125 a3pn250 known good die 34 52 71 71 68 qn48 34 qn68 49 vq100 71 71 68 notes: n se ees o ot sot ts ete o e estes sot o to etes ee to te o o tseets ses es
12 www .microsem i.com /soc proasic3 notes: 1 aes is not available for cortex-m1 proasic3l devices. 2 for the a3pe3000l, the pq208 package has six cccs and two plls. proasic3l balancing low power, performance and low cost proasic3l fpgas feature 40 percent lower dynamic power and 90 percent lower static power than the previous generation proasic3 fpgas and orders of magnitude lower power than sram competitors, combining dramatic ally reduced power consumption with up to 350 mhz operation. the proasic3l family also supports the free implementation of an fpga-optimized 32-bit arm cortex-m1 processor, enabling system designers to select microsemis fash fpga solution that best meets their speed and power design requirements, regardless of application or volume. optimized software tools using power-driven layout (pdl) provide instant power reduction capabilities. i/os per package proasic3l low power devices a3p250l a3p600l a3p1000l a3pe3000l cortex-m1 devices m1a3p600l m1a3p1000l m1a3pe3000l 250,000 600,000 1,000,000 3,000,000 versatiles (d-fip-fops) 6,144 13,824 24,576 75,264 ram (1,024 bits) 36 108 144 504 4,608-bit blocks 8 24 32 112 flashrom kbits (1,024 bits) 1 1 1 1 as-protected sp 1 yes yes yes yes ntegrated p in cccs 2 1 1 1 6 versanet globals 18 18 18 18 i/o banks 4 4 4 8 maimum ser /os packaged device 157 235 300 620 package pins vq vq100 pq208 fg144, fg256 pq208 fg144, fg256, fg484 pq208 fg144, fg256, fg484 pq208 fg324, fg484, fg896 proasc3 devices a3p250l a3p600l a3p1000l a3pe3000l cortex-m1 devices m1a3p600l m1a3p1000l m1a3pe3000l differential differential differential differential vq100 68 13 pq208 151 34 154 35 154 35 147 65 fg144 97 24 97 25 97 25 fg256 157 38 177 43 177 44 fg324 221 110 fg484 235 60 300 74 341 168 fg896 620 310 ? low power 1.2 v to 1.5 v ? 700 mbps ddr, lvds ? up to 350 mhz system performance ? enhanced i/o features ? embedded sram and nvm ? confguration memory error ? isp and security ? flash*freeze technology for lowest power ? reprogrammable fash technology ? cccs and plls
13 www .microsem i.com /soc military proasic3/el / military proasic plus military proasic3/el low power fpgas for military applications building on the successful heritage of the military proasic plus family, military proasic3 fpgas offer higher performance, greater density and more memory, while at the same time offering high reliability combined with compact single-chip logic integration, live at power-up operation and reprogrammability. military proasic3/el fpgas have demonstrated immunity to confguration upsets caused by atmospheric neutrons. ? supports single-voltage system operation ? 3,000,000 system gates ? up to 504 kbits of true dual-port sram ? live-at-power-up level 0 support ? isp protected using on-chip 128-bit advanced encryption ? standard (aes) decryption via jtag (ieee 1532Ccompliant) military proasic3 devices military proasic3 devices a3p250 a3pe600l a3p1000 a3pe3000l cortex-m1 devices 1 m1a3p1000 m1a3pe3000l system gates 250,000 600,000 1,000,000 3,000,000 versatiles (d-fip-fops) 6,144 13,824 24,576 75,264 ram (1,024 bits) 36 108 144 504 4,608-bit blocks 8 24 32 112 flashrom (kbits) 1 1 1 1 aes-protected isp 2 yes yes yes yes integrated pll in cccs 1 6 1 6 versanet globals 18 18 18 18 i/o banks 4 8 4 8 maximum user i/os 68 270 154 620 package pins vq pq fg 100 484 208 144 484, 896 notes: ee to te ote ot e o oe oto s ot e o ee o ees military proasic plus reprogrammable, nonvolatile military fpgas military proasic plus is the industrys frst nonvolatile, reprogrammable fpga with testing covering the full military temperature range (C55oc to 125oc), with available mil-std-883 class b screening. the fash-based reprogrammable interconnect used in microsemis proasic plus fpgas has been proven to be immune to confguration changes caused by atmospheric neutrons, which plague sram-based fpgas in high-reliability applications. military proasic plus devices military proasic plus devices apa300 apa600 apa1000 maximum system gates 300,000 600,000 1,000,000 tiles (registers) 8,192 21,504 56,320 ram kbits (1,024 bits) 72 126 198 ram blocks (256x9) 32 56 88 lvpecl 2 2 2 pll 2 2 2 global networks 4 4 4 maximum clocks 32 56 88 maximum user i/os 290 454 712 jtag isp yes yes yes pci yes yes yes package pins cq cg 208, 352 208, 352 624 208, 352 624
15 14 www .microsem i.com /soc www .microsem i.com /soc 3x3 uc36 0.40 4x4 uc81 0.40 5x5 cs81 0.50 6x6 cs121 0.50 6x6 qn48 0.40 8x8 cs196 0.50 8x8 qn68 0.40 8x8 qn132 0.50 8x8 cs201 0.50 10x10 qn108 0.50 10x10 qn180 0.50 10x10 cs281 0.50 11x11 cs288 0.50 13x13 fg144 1.00 14x14 cs289 0.80 14x14 vq100 0.50 14x14 vq128 0.40 17x17 fg256 1.00 19x19 fg324 1.00 20x20 tq144 0.50 20x20 vq176 0.40 23x23 fg484 1.00 27x27 fg676 1.00 28x28 pq208 0.50 31x31 fg896 1.00 32.5x32.5 cg624 1.27 29.21x29.21 cq208 0.50 48x48 cq352 0.50 23 34 52 52 49 66 66 34 49 81 120 120 77 101 60 96 80 157 112 96 157 71 108 137 37/9 (16) 60/16 (20) 75/22 (20) 60 133 84 212 97 212 71 100 133 135 117 161 113 60 143/35 87/19 65/15 (24) 97/24 68/13 114/37 (24) 157/38 93/26 (24) 151/34 158 248 143/35 97/25 178/38 194/38 151/34 135 117 204 113 215/53 97/25 119/58 (40) 177/43 172/86 (40) 235/60 95/46 (40) 154/35 440 158 248 215/53 97/25 177/44 300/74 154/35 440 158 248 165/79 270/13 5 147/65 119/58 (40) 223/109(40) 280/139 252/126(40) 444/222 147/6 5 221/110 341/168 147/65 620/310 70 91 size (mm) name pitch (mm) smartfusion fusion ext. t emp. fusion igloo/e igloo nano igloo plus pr oasic3/e pr oasic3 nano pr oasic3l military pr oasic3/el military pr oasic plus agln010 a3pn010 agln020 a3pn020 agl030 agln030 aglp030 a3p030 a3pn030 a2f060 agl060 agln060 aglp060 a3p060 a3pn060 afs090 a2f200 a2f500 agl125 agln125 aglp125 a3p125 a3pn125 afs250 agl250 agln250 a3p250 a3pn250 a3p250l a3p250 ap a300 agl400 a3p400 afs600 afs600 agl600 a3p600 a3p600l ap a600 agl1000 a3p1000 a3p1000l a3p1000 ap a1000 agle600 a3pe600 a3pe600l afs1500 afs1500 a3pe1500 agle3000 a3pe3000 a3pe3000l a3pe3000l i/o table i/o table notes: # / # structure shows single-ended/double-ended i/os. fusion and ext. temp. fusion i/o counts are in italics. value in parentheses for fusion is analog i/os. smartfusion values are total analog, mss and fpga i/os. please refer to the soc products groups website at www.microsemi.com/soc and appropriate product datasheets for the latest device information and valid ordering codes. i/o table go to www.microsemi.com/soc for information regarding previous generations of fash and antifuse fpgas.
16 www .microsem i.com /soc fpga packages fpga packages cs121 f igloo proasic3 p s 6x6 mm h 0.90 mm p 0.50 mm cs81 f igloo igloo nano p s 5x5 mm h 0.80 mm p 0.50 mm uc81 f igloo igloo nano p s 4x4 mm h 0.80 mm p 0.40 mm uc36 f igloo nano p s 3x3 mm h 0.80 mm p 0.40 mm fg896 f iglooe 1 proasic3e 1 proasic3l 1 military proasic3/el 1 p s 31x31 mm h 2.23 mm p 1.00 mm ? fg144 f igloo 1 proasic3 1 proasic3l 1 military proasic3/el 1 p s 13x13 mm h 1.45 mm p 1.00 mm fg256 f smartfusion fusion 1, 3, 4 igloo 1 iglooe proasic3 1, 2 proasic3e 2 proasic3l 1 p s 17x17 mm h 1.60 mm p 1.00 mm fg676 f proasic3e 1 fusion 1 p s 27x27 mm h 2.23 mm p 1.00 mm fg484 f smartfusion fusion 1, 3 igloo 1 iglooe 1 proasic3 1, 2 proasic3e 1, 2 proasic3l 1 military proasic3/el 1 p s 23x23 mm h 2.23 mm p 1.00 mm fg324 f proasic3e 1 proasic3l 1 p s 19x19 mm h 1.63 mm p 1.00 mm cs196 f igloo p s 8x8 mm h 1.11 mm p 0.50 mm cs201 f igloo plus p s 8x8 mm h 0.89 mm p 0.50 mm cs281 f igloo 1 igloo plus p s 10x10 mm h 1.05 mm p 0.50 mm cs288 f smartfusion p s 11 x 11 mm h 1.05 mm p 0.50 mm cs289 f igloo plus p s 14x14 mm h 1.20 mm p 0.80 mm qn108 f fusion p s 8x8 mm h 0.75 mm p 0.50 mm qn68 f igloo igloo nano proasic3 proasic3 nano p s 8x8 mm h 0.90 mm p 0.40 mm qn48 f igloo igloo nano proasic3 proasic3 nano p s 6x6 mm h 0.90 mm p 0.40 mm qn132 f igloo proasic3 p s 8x8 mm h 0.75 mm p 0.50 mm qn180 f fusion p s 10x10 mm h 0.75 mm p 0.50 mm key: f C family bs C package body size excluding leads ps C overall package dimensions including package leads h C package thickness p C pin pitch / ball pitch notes: 1 includes cortex-m1 devices. 2 fg256 and fg484 are footprint-compatible for proasic3 and proasic3e. 3 pigeon point devices are only offered in fg484 and fg256. 4 microblade devices are only offered in fg256.
17 www .microsem i.com /soc fpga packages refer to the package mechanical drawings document located at www.microsemi.com/soc/documents/pckgmechdrwngs.pdf for more information concerning package dimensions. tq144 f proasic3 b s 20x20 mm p s 22x22 mm h 1.40 mm p 0.50 mm vq100 f igloo 1 igloo nano proasic3 1 proasic3 nano proasic3l military proasic3/el 1 b s 14x14 mm p s 16x16 mm h 1.00 mm p 0.50 mm pq208 f smartfusion fusion 1 proasic3 1 proasic3e 1 proasic3l 1 military proasic3/el 1 bs 28x28 mm ps 30.6x30.6 mm h 3.40 mm p 0.50 mm vq128 f igloo plus bs 14x14 mm ps 16x16 mm h 1.00 mm p 0.40 mm vq176 f igloo plus bs 20x20 mm ps 22x22 mm h 1.00 mm p 0.40 mm cq352 f military proasic plus p s 48x48 mm h 2.67 mm p 0.50 mm cq208 f military proasic plus p s 29.21x29.21 mm h 2.67 mm p 0.50 mm cg624 f military proasic plus p s 32.5x32.5 mm h 4.94 mm p 1.27 mm
18 www .microsem i.com /soc axcelerator ? 500+ mhz internal performance ? 500+ mhz embedded fifos ? pll output up to 1 ghz and 8 plls per device ? 6 levels of logic at 156+ mhz ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/os8 banks per chip ? 8 global clocks per device ? 4.5 kbits variable-aspect ram blocks with built-in fifo control ? secure programming technology is designed to prevent reverse engineering and design theft axcelerator axcelerator devices i/os per package axcelerator device ax125 ax250 ax500 ax1000 ax2000 pq 208 208 bg 729 fg 256, 324 256, 484 484, 676 484, 676, 896 896, 1152 cq 208, 352 208, 352 352 256, 352 cg/lg 624 624 first for speed and performance the axcelerator fpga family is a single-chip, nonvolatile solution offering high performance and unprecedented design security at densities of up to 2 million equivalent system gates. utilizing the ax architecture, axcelerator devices have several system-level features, such as embedded sram (with embedded fifo control logic), plls, segmentable clocks, chip-wide highway routing, and carry logic. based upon 0.15 m, seven-layers-of-metal cmos antifuse process technology, 350 mhz system performance. axcelerator device ax125 ax250 ax500 ax1000 ax2000 capacity (in equivalent system gates) 125,000 250,000 500,000 1,000,000 2,000,000 typical gates 82,000 154,000 286,000 612,000 1,060,000 register (r-cells) 672 1,408 2,688 6,048 10,752 combinatorial (c-cells) 1,344 2,816 5,376 12,096 21,504 maximum flip-flops 1,344 2,816 5,376 12,096 21,504 number of core ram blocks 4 12 16 36 64 total bits of core ram 18,432 55,296 73,728 165,888 294,912 clocks (hardwired) 4 4 4 4 4 clocks (routed) 4 4 4 4 4 plls 8 8 8 8 8 i/o banks 8 8 8 8 8 maximum user i/os 168 248 336 516 684 maximum lvds channels 84 124 168 258 342 total i/o registers 504 744 1,008 1,548 2,052 speed grades std., C1, C2 std., C1, C2 std., C1, C2 std., C1, C2 std., C1, C2 temperature grades c, i c, i, m c, i, m c, i, m c, i, m
19 www .microsem i.com /soc sx-a sx-a sx-a devices i/os per package sx-a device a54sx08a a54sx16a a54sx32a a54sx72a typical gates 8,000 16,000 32,000 72,000 system gates 12,000 24,000 48,000 108,000 logic modules 768 1,452 2,880 6,036 combinatorial cells 512 924 1,800 4,024 dedicated flip-flops 256 528 1,080 2,012 maximum flip-flops 512 * 990 1,980 4,024 maximum user i/os 130 180 249 360 global clocks 3 3 3 3 quadrant clocks 0 0 0 4 boundary scan testing yes yes yes yes 3.3 v / 5 v pci yes yes yes yes input set-up (external) 0 ns 0 ns 0 ns 0 ns speed grades Cf, std., C1, C2 Cf, std., C1, C2 Cf, std., C1, C2 Cf, std., C1, C2 temperature grades c, i, a, m c, i, a, m c, i, a, m, b c, i, a, m, b sx-a devices a54sx08a a54sx16a a54sx32a a54sx72a pq 208 208 208 208 vq tq 100, 144 100, 144 100, 144, 176 bg 329 fg 144 144, 256 144, 256, 484 256, 484 cq 84, 208, 256 208, 256 reducing the cost of performance the sx-a family of fpgas offers a cost-effective, single-chip solution for low-power, high-performance designs. sx-a devices can be used to generate system-wide savings by integrating multiple functions into a single-chip solution. providing a combination of performance, security, and low power, sx-a fpgas decrease the premium for performance while providing a solution that is highly resistant to reverse engineering. ? 12,000 to 108,000 usable system gates ? 250 mhz system performance ? 350 mhz internal performance ? hot-swap compliant i/os ? power-up and power-down friendly (no sequencing required for supply voltages) ? 66 mhz, 64-bit 3.3 v / 5.0 v pci performance (supporting target, master and master/target) ? 2.5 v, 3.3 v, and 5.0 v mixed-voltage support ? 100% resource utilization with 100% pin locking
20 www .microsem i.com /soc mx ? single-chip asic alternative ? 3,000 to 54,000 system gates ? up to 2.5 kbits confgurable dual-port sram ? fast wide-decode circuitry ? up to 202 user-programmable i/o pins ? high performance mixed-voltage solution ? pci compliant ? contains embedded dual-port sram modules ? qml certifcation ? ceramic devices available to dscc sm mx mx devices i/os per package mx devices a40mx02 a40mx04 a42mx09 a42mx16 a42mx24 a42mx36 pl 44, 68 44, 68, 84 84 84 84 pq 100 100 100, 160 100, 160, 208 160, 208 208, 240 vq 80 80 100 100 tq 176 176 176 cq 208, 256 bg 272 the price/performance leader at 5.0 v featuring very low power consumption and the industrys highest design security, mx fpgas offer designers a reliable, single-chip asic alternative. mx devices provide high performance while shortening the system design and development cycle. offering an effcient, fexible 5.0 v architecture, mx is an ideal high-volume platform for integrating your legacy plds into a single device. example applications include high-speed controllers and address decoding, peripheral bus interfaces, dsp, and coprocessor functions. mx devices a40mx02 a40mx04 a42mx09 a42mx16 a42mx24 a42mx36 system gates 3,000 6,000 14,000 24,000 36,000 54,000 sram bits 2,560 sequential 348 624 954 1,230 combinatorial 295 547 336 608 912 1,184 decode 24 24 clock-to-out 9.5 ns 9.5 ns 5.6 ns 6.1 ns 6.1 ns 6.3 ns sram modules (64x4 or 32x8) 10 dedicated flip-flops 348 624 954 1,230 clocks 1 1 2 2 2 6 maximum flip-flops 147 273 516 928 1,410 1,822 user i/os (maximum) 57 69 104 140 176 202 pci yes yes boundary scan test (bst) yes yes speed grades Cf, std., C1, C2, C3 Cf, std., C1, C2, C3 Cf, std., C1, C2, C3 Cf, std., C1, C2, C3 Cf, std., C1, C2, C3 Cf, std., C1, C2, C3 temperature grades c, i, m, a c, i, m, a c, i, m, a c, i, m, a c, i, m, a c, i, m, a, b
21 www .microsem i.com /soc fpga design flashpr o4, ulink, j-link har dwar e interfaces mss configuration ? analog configuration mss configurator * design entry and ip libraries simulation and synthesis compile and layout timing and power analysis hardware debug embedded design softwar e ide (softconsole, keil, iar) drivers and sample projects application development build project simulation software debug microsemi design environment design environment for microsemi flash devices * mss confgurator is specifc to the smartfusion design fow. microsemis libero ? integrated design environment (ide) is a comprehensive software toolset for designing with all microsemi fpgas. libero ide includes industry-leading synthesis, simulation and debug tools from synopsys ? and mentor graphics ? , as well as innovative timing and power optimization and analysis. microsemis smartdesign tool simplifes the use of microsemi ip in user designs as well as offering a simple way to build on-chip processors with custom peripherals. most microsemi ip cores are now included by default in libero ide as either obfuscated or rtl versions, depending on the license selected. for embedded designers, microsemi offers free softconsole eclipse-based ide for use with arm cortex-m1, cortex-m3 and core8051s, as well as evaluation versions from keil ? and iar systems ? . full versions are available from respective suppliers. for smartfusion csocs, the mss confgurator creates a bridge between the fpga fabric and embedded designs, so device confguration can be easily shared among multiple developers. the mss confgurator allows the designer to choose peripherals, assign confguration settings and change i/o attributes. most importantly, the memory map is automatically generated according to the users selections, along with all the required frmware for the selected confguration. the memory map and frmware are imported into the software project, whether it is gnu, keil or iar. fpga design support embedded design support platform support libero ide licenses gold (free) platinum platinum evaluation standalone device support all families up to 1,500,000 gates all devices all devices all devices microsemi ip obfuscated rtl obfuscated rtl synthesis synplify ? pro ae x x x simulation modelsim ? ae x x x debug identify ? ae x x x microsemi debug x x x x program file x x x microsemi keil iar systems softconsole keil mdk embedded workbench ? free versions from microsemi free with libero ide 32 k code limited 32 k code limited available from vendor n/a full version full version compiler gnu gcc realview ? c/c++ iar arm compiler debugger gdb debug vision debugger c-spy ? debugger instruction set simulator no vision simulator yes debug hardware flashpro4 ulink ? 2 or ulink-me j-link ? or j-link lite tool libero ide softconsole keil iar flashpro windows ? xp professional now now now now now windows vista business and windows 7 now now now now now redhat linux ws 5.0, 5.2 now n/a n/a n/a n/a
22 www .microsem i.com /soc development kits ? supports smartfusion development, including arm cortex-m3, fpga and programmable analog ? free one-year libero ide software and gold license with softconsole for program and debug ? 5 v power supply and international adapters ? two usb cables and low cost programming stick ? users guide, tutorial and design examples ? pcb schematics, layout fles and bom ? board features - ethernet, ethercat, can, uart, i 2 c and spi interfaces - usb port for hyperterminal - usb port for programming and debug - j-link header for debug - mixed signal and a2f500 digital expansion header - extensive off-chip memory - refer to www.microsemi.com/soc for a full list of features ? supports smartfusion csoc evaluation, including arm cortex-m3, fpga and programmable analog ? free one-year libero integrated design environment (ide) software and gold license with softconsole for program and debug ? usb programming built into board ? two usb cables ? users guide, tutorial and design examples ? printed circuit board (pcb) schematics, layout fles and bill-of-materials (bom) ? board features - ethernet interface - usb port for power and hyperterminal - usb port for programming and debug - j-link header for debug - mixed signal header - spi fash C off-chip memory - reset and 2 user switches, 8 leds - pot for voltage / current monitor - temperature monitor - organic light-emitting diode (oled) ordering codes supported devices price a2f500-dev-kit a2f500m3g-fgg484 $ 999 ordering code supported device price a2f-eval-kit a2f200m3f-fgg484 $ 99 ? supports debug access to the mixed signal header of the smartfusion evaluation kit and smartfusion development kit ? 4 1/2 plastic standoffs and 4 plastic screws to match development kit height ? sold standalone ? board features - test points for signal probing - mixed signal header for daughter card support - 100 mil header for wire-wrapped or soldered signals 10/100 ethernet interface regulators usb program and debug interface smartfusion device user sw2 usb power and usb-uart interface potentiometer reset switch 5 debug i/os 8 user leds debug select jtag select oled display rvi - header spi-flash memory pub switch vrpsm voltage option 20 mhz crystal 32.768 khz crystal user sw1 mixed signal header 4nbsu'vtjpo&wbmvbujpo,ju .jyfe4jhobm%bvhiufs$bse directc header board reset switch power jack memory device configuration headers aglp dip switch aglp125v5- csg289 igloo plus header 10/100 ethernet phy rj45 connector for 10/100 ethernet power switch dacout/ adc headers rj45 connectors for ethercat ports smartfusion csoc db9 connector for can0 sram (3.3 v) can transceivers db9 connector for can1 a2f500 connector psram (1.8 v) lcps connector dip switch jtag_sel switch jtag chain configuration header 1.5 v header pub switch rs485 transceiver db9 connector for rs485 (uart1) 50 mhz oscillator spi headers i 2 c headers usb connector for uart0 oled push-button switches realview ? header jtag mux ethercat phys dac0 and dac1 callibration pots for 15 v bipolar outputs pot for current monitor mixed signal header ethercat asic 4nbsu'vtjpo%fwfmpqnfou,ju ordering code supported device price mixed-signal-dc no microsemi device $ 55 mixed signal connector test points 100 mil connector
23 www .microsem i.com /soc development kits mpm 9 v jack mpm power switch power supply regulator reg1 - reg4 interrupt switches (sw8, sw11, sw16, sw15) mixed signal header power supply regulator reg1 - reg4 potentiometers power supply regulators r1 - r4 leds mpm daughter card motor control development kit ? supports power management design with the smartfusion evaluation kit and smartfusion development kit ? mpm design example implements confgurable power management in smartfusion csoc ? graphical confguration dialog ? in-system reconfgurable ? 9 v power supply ? board features - 4 power supply regulators - 4 potentiometers to control regulators - 4 power supply regulator interrupt switches - 4 power supply regulator status leds - mixed signal header connector connects to smartfusion board ? circuitry on board accommodates drivers for up to 4 pmsm motors (1 supplied with kit) ? one pmsm motor with hall sensor and encoder included ? reference design supporting multiple operation modes ? pc interface for defning velocity, torque and other parameters for up to four motors in real-time over an ethernet connection ? 18 v power supply ? mains power supply with international adapter ? cross over cable ? schematics and design fles available ? users guide ? five reference designs including c source code and rtl ? commutation in trapezoidal mode using hall effect sensor feedback ? sinusoidal using hall effect sensor feedback - commutation starts in trapezoidal mode and switches to sinusoidal when suffcient speed is achieved ? sinusoidal with hall effect encoder feedback - commutation starts in trapezoidal mode and switches to sinusoidal mode on frst edge of hall sensor input using incremental encoder ? sensorless trapezoidal - uses back-emf to generate six-step commutation feedback ordering code supported device price mpm-dc-kit no microsemi device $ 299 ordering code description price 3/3-* motor control kit including reference designs and 1 motor $ 2,499 .0503$0/530-4/4 motor control reference designs $ 499 .05034 additional 3 motors $ 185
24 www .microsem i.com /soc development kits ordering code supported device price agln-nano-kit* agln250v2-vqg100 $ 99 ? supports basic igloo nano low power fpga design, including flash*freeze mode ? free one-year libero ide software and gold license ? low-cost programming stick (lcps) ? two usb cables ? kit users guide, libero ide tutorial and design examples ? pcb schematics, layout fles and bom ? board features - all i/os available for external connections - full current measurement capability of independent i/o banks and vcc - usb connection for usb-to- serial (rs232) interface for hyperterminal or power - 20 mhz clock oscillator - leds and switches for simple inputs and outputs - ability to switch vcore from 1.2 v to 1.5 v - rohs compliant 20 mhz clock oscillator igloo nano fpga i/o te st pin headers usb interface 5 v wa ll jack jumpers for v oltage options jumper for battery option 4 push-button switches lcps connector push-button reset switch flash*fr eeze switch curr ent measur ement headers 8 user leds 8 dip switches jumpers to isolate user leds, push-button switches, dip switches for i/o te st pins igloo nano starter kit note: * replaces -z version of the nano starter kit. ? supports basic proasic3 fpga design and lvds i/o usage ? free one-year libero ide software and gold license ? flashpro3 or flashpro4 programmer ? 9 v power supply and international adapters ? kit users guide, libero ide tutorial and design examples ? pcb schematics, layout fles and bom ? board features - eight i/o banks with variety of voltage options - oscillator for system clock or manual clock option - leds and switches for simple inputs and outputs - lcd display module - two cat5e rj45 connectors for high-speed lvds communications - all i/os available for external connections - not rohs compliant w all mount power interboard isp connector lcd display module ca t5e rj45 connectors for l vds communications sma for optional extern al oscillator removable shunts to isolate all i/os for pr ototyping removable shunts to isolate all i/os for pr ototyping oscillator for system clock manual clock option flashpr o3 isp connector pr oasic3/e in pq208 package 4 switches every pq208 pin accessible for pr ototyping 8 leds removable shunts to isolate all i/os for pr ototyping proasic3 starter kit ordering codes supported devices price 3* a3pe1500-pq208 $ 665 ? supports royalty-free, industry- standard arm cortex-m1 or 8051s development ? free one-year libero ide software and gold license with softconsole for program and debug ? low-cost programming stick (lcps) ? 5 v power supply and international adapters ? two usb cables ? kit users guide, libero ide tutorial and design examples ? pcb schematics, layout fles and bom ? board features - 512 kb sram, 2 mb spi fash memory provided on board - 10/100 ethernet and i 2 c interfaces - usb-to-uart connection for hyperterminal on a pc - built-in voltage, current and temperature monitor and voltage potentiometer - mixed signal interface - blue oled 96x16 pixel display - dynamic reconfgurable analog and fash memory - flashpro3 and realview debug interface - rohs compliant user leds lcps connector oled mixed signal test pins mixed signal header push-button switch fusion fpga spi flash ethernet interface realview header push- button switch interface connector usb interface push- button pub two i 2 c interfaces potentiometer push- button reset sram 5 v wall jack ethernet leds jumpers for internal or external regulator fusion embedded development kit ordering code supported device price * m1afs1500-fgg484 $ 250
25 www .microsem i.com /soc development kits ? allows users to evaluate the functionality of microsemis core1553brm without having to create a complete mil-std-1553b compliant system ? fusion advanced development kit with two 9 v power supplies ? core1553 daughter card ? users guide, tutorial and design example ? pcb schematics, layout fles and bom ? purchasing the kit gives the owner the right to the programming fle of the demo, but not an evaluation of the ip. the ip evaluation or purchase is quoted separately. ? board features - mil-std-1553b transceiver, two transformers and two concentric twinax connectors included on the core1553 daughter board ~ mil-std-1553b concentric twinax connectors are center pin signal high and cylindrical contact signal low ~ connectivity is mil-c-49142 compliant ~ evaluate and develop medium speed on-board data communications bus solutions for mil-std-1553b / uk def-stan 00-18 (pt.2) / nato stanag 3838 avs / avionic standards coordinating committee air-std 50/2 - can bus interface support - connector to arinc 429 daughter board (core429-sa) fusion advanced development kit core1553-sa core1553 development kit hardware summary ordering code description price 3* core1553 development kit $ 3,620 $034 core1553 daughter card $ 2,900 .477,5183 m1afs-adv-dev-kit with two 9 v power packs $ 750 family ordering code name device price power smartfusion -* smartfusion evaluation kit a2f200m3f-fgg484 $ 99 usb smartfusion * smartfusion development kit a2f500m3g-fgg484 $ 999 5 v smartfusion mpm-dc-kit mpm daughter card none $ 299 9 v smartfusion mixed-signal-dc mixed signal daughter card none $ 55 n/a fusion * fusion embedded development kit m1afs1500-fgg484 $ 250 usb / 5 v fusion -* fusion starter kit afs600-fg256 $ 500 9 v fusion *3 fusion advanced development kit m1afs1500-fgg484 $ 750 9 v igloo agln-nano-kit* igloo nano starter kit agln250v2-zvqg100 $ 99 usb igloo agl-icicle-kit igloo icicle evaluation kit agl125v2-qng132 $ 150 usb igloo (--* igloo plus starter kit aglp125v2-csg289 $ 299 5 v igloo (-* arm cortex-m1 igloo development kit m1agl1000v2-fgg484 $ 550 5 v proasic3 3* proasic3 starter kit a3pe1500-pq208 $ 665 9 v proasic3 -* arm cortex-m1 proasic3l development kit M1A3P1000L-FGG484 $ 550 5 v *most recommended kit for each product family microsemi offers hardware choices for terrestrial products. most popular kits are listed in the table and shown in further detail in this section. full details of these kits can also be found online with users guides and accompanying tutorials.
26 www .microsem i.com /soc programmers ordering code price silicon-sculptor 3 $ 4,330 ? supports in-system programming ? supports ieee 1149 jtag programming through stapl ? supports ieee 1532 ? uses flashpro software, available as part of libero ide or standalone ? free software updates ? usb connection to pc ? operating systems - windows xp professional (sp2 recommended) - windows 2000 professional (sp4 recommended) mbti1spo4tufn1(1sphsbnnfs ? programs all microsemi packages, including pl, pq, vq, qn, bg, fg, and cs ? universal microsemi socket adapters ? use with silicon sculptor software ? security fuse can be programmed to secure the devices ? includes self-test to test its own hardware ? protection features - overcurrent shutdown - power failure shutdown - esd protection - esd wrist straps with banana jacks (included as standard) ? operating systems - windows xp professional (sp2 recommended) - windows 2000 professional (sp4 recommended) silicon sculptor 3 fpga programmer directc directc v2.3 is a set of c code designed to support embedded ndspqspdfttpsoctfottfnqspsnnogps-001sp4$o fusion families. to use directc v2.3, you must make some minor modifcations pfqspwftpsdfdpffofdftts1odpnqmfftpsdf dpfof1pffspdsffcosfyfdcmf5fsfttfn ntdpoondspqspdfttpsnonncftpg3.5 interface to the target device from the microprocessor and access to the programming data to be used for programming the fpga. access to programming data could be provided by a telecommunications link for most remote systems. pompsfd$tpsdfmftofdpnqmfftfstf ndsptfndpntpdqspdtssfqspsnfcsfddfgmtqy stapl player if-mfsdocftfeupqspsnuisefofsupotiefdfttdi t*(-sp*oetpooeoufsqsfutuifdpoufoutpg-mf xiditfofsufec-cfsp*tpguxsfuppmtifmfdpouotogpsnupo about the programming of microsemi fash-based devices, as well as the 5tdodogpstomffwdf5fgpsnt$tos opotf4os5fto1spsnno-of451-gpsn pssfofspofwdftopff451-1mfsmmoptqqps tfsmpopgfmt30.opsmmtqqps4nsstffocmftmdpo 5f451-1mfssftf451-mfofyfdftfmftqspsnno otsdpotfdtfmmqspsnnofmtsfof451-mff 451-1mfstfmgtdpnqmffmfwdfofqfofoopfspstf system does not need to implement any programming algorithm details; the 451-mfqspwftmmpgffmt 5ffggfsfodftcfffofsfd$of451-qmfsnfptsf in the memory footprint in the microprocessor and amount of data to transmit. the directc option requires more code space on the processor, but as a result less data has to be transmitted to perform programming. on the other of451-qmfsdpnnodftcpfogpsnpopcfqspsnnf and the intelligence needed to perform programming. so the code footprint is smaller but the amount of data to transmit will be larger. one advantage of f451-qmfsnfptgqftsfsfsfpfqspsnno mpsnf451-nfppftopsfsfofdpfofqspdfttps but the directc would require new code for the processor. 1spsnnofwdfto4tfn6to.dspqspdfttps mpfmt1spqspsnnfsdoqfsgpsnottfnqspsnnopftsfsftqfddffspcfdpoofdffyfsommpsfynqmfg psttfnmsftfyfsomdpnnodpowmcmfspndspqspdfttpsofsgdfpnqsfgfspwffqspdfttpsqfsgpsnfottfn programming. this can be done in two ways. for adapter modules, refer to www.microsemi.com/soc/products/hardware/program_debug/ss/modules.aspx ordering code price flashpro4 $ 49
27 www .microsem i.com /soc intellectual property cores microsemi ip cores tiles obfuscated core rtl core core10/100 10/100 mbps ethernet mac with host controller (ahb/apb option available) 7,254 free libero gold purchase core1553bbc mil-std-1553b bus controller (bc) 2,331 purchase purchase core1553brm mil-std-1553b bus monitor only 3,016 purchase purchase core1553brm mil-std-1553b combined remote terminal (rt), bus controller, and bus monitor (bm) 6,787 purchase purchase core1553brt mil-std-1553b remote terminal 1,612 purchase purchase core429 arinc 429 bus interface (1 receive channel) 740 purchase purchase core429 arinc 429 bus interface (1 transmit channel) 563 purchase purchase corepcif pci specifcation 2.3 bus controller with fifo support (66/64 target and master) 3,808 purchase purchase corepcif pci specifcation 2.3 bus controller with fifo support (33/32 target) 996 purchase purchase core16550 universal asynchronous receiver/transmitter with or without fifo 979 libero gold libero platinum core3des 3des encryption and decryption 1,413 libero gold libero platinum core8051s 8-bit microprocessor, 100% asm51 compatible, confgurable peripherals, ahb bus compliant 2,500 libero gold libero platinum coreabc low-gate-count controller for the apb 241 libero gold libero platinum coreaes128 aes encryption and decryption 5,193 libero gold libero platinum coreahb multi-master advanced high performance bus (ahb) 1,300 libero gold libero platinum coreahb2apb ahb to advanced peripheral bus (apb) bridge 250 libero gold libero platinum coreahblite single-master ahb 700 libero gold libero platinum coreahbnvm on-chip flash memory controller with ahb interface 396 libero gold libero platinum coreahbsram on-chip sram memory controller with ahb interface 236 libero gold libero platinum coreai analog interface core (maximum confguration) 460 libero gold libero platinum coreapb apb 125 libero gold libero platinum corecfi common flash interfacetypical confguration 600 libero gold libero platinum corecordic coordinate rotational digital computer core (bit-serial architecture) 450 libero gold libero platinum coreddr high performance double data rate (ddr) sdram controller 1,748 libero gold libero platinum coredes des encryption and decryption 1,271 libero gold libero platinum corefmee flash memory endurance extender (typical confguration) 541 libero gold libero platinum coregpio general-purpose input/output controller with apb interface 100 libero gold libero platinum corei2c i 2 c master/slave interface 658 libero gold libero platinum coreinterrupt coremp7 interrupt controller 68 libero gold libero platinum corelpc intel low pin count interface for fusion/igloo/pa3 (serirq disabled) 340 libero gold libero platinum corememctrl off-chip memory controller with ahb interface 100 libero gold libero platinum corepwm pulse width modulation core (typical confguration) 650 libero gold libero platinum coresdlc synchronous data link controller 1,286 libero gold libero platinum coresdr high performance single data rate (sdr) sdram controller 1,350 libero gold libero platinum coresmbus system management bus controller (master/slave confguration) 1,078 libero gold libero platinum coresmbus system management bus controller (slave-only confguration) 733 libero gold libero platinum corespi serial peripheral interface (combined mode) 330 libero gold libero platinum coretimer 16- or 32-bit timer with apb interface 310 libero gold libero platinum coreuart universal asynchronous receiver/transmitter 337 libero gold libero platinum coreuart_apb universal asynchronous receiver/transmitter with apb interface 300 libero gold libero platinum corewatchdog watchdog timer with apb interface 280 libero gold libero platinum cortex-m1 high performance 32-bit fpga-optimized processor (pre-placed design block) 4,300 libero gold libero platinum corefft fast fourier transform core generator (1,024 points) 9,030 web only web only corefft fast fourier transform core generator (256 points) 7,364 web only web only corefir finite impulse response core generator (confguration 1) 583 web only web only note: additional cores and confgurations can be found on the website and in core handbooks. intellectual property cores flashpro4 in-system fpga programmer
?2011 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. 55700040-9/10.11 microsemi corporate headquarters one enterprise drive, aliso viejo, ca 92656 within the usa: (800) 713-4113 outside the usa: (949) 221-7100 fax: (949) 756-0308 www.microsemi.com microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. products include high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquartered in aliso viejo, calif. learn more at www.microsemi.com. you may be interested in: space product catalog: www.microsemi.com/soc/documents/spaceprodcat_pib.pdf solutions and ip catalog: www.microsemi.com/soc/documents/ippib.pdf microsemi soc products group 2061 stierlin court, mountain view, ca 94043-4655 usa phone: 650.318.4200 www.microsemi.com/soc

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